The present disclosure relates to a semiconductor memory device, and more particularly to an internal voltage compensation circuit, capable of adjustably compensating for the level of an internal voltage corresponding to two different external voltages in a power up section.
Generally, a power up signal generating circuit of a semiconductor device has a function of initializing the semiconductor device. Meanwhile, in order to operate the semiconductor device, an external voltage VDD is supplied to the semiconductor device from an external device. The level of the external voltage VDD is increased from 0[V] to a target voltage level with a predetermined slope. In this case, if all circuits of the semiconductor device are directly supplied with the external voltage VDD, the circuits may operate erroneously due to the influence of the rising external voltage. Accordingly, in order to prevent the circuits from erroneously operating, the semiconductor device employs the power up signal generating circuit and enables a power up signal, such that the external voltage VDD is supplied to the circuits after the external voltage VDD becomes a stable level. The semiconductor device is initialized through the above power up operation.
Meanwhile, in order to turn on an NMOS transistor mainly employed in a DRAM memory cell, a voltage higher than a source voltage by at least a threshold voltage Vt must be applied to a gate. However, generally, since the maximum voltage applied to the DRAM has the level of the external voltage VDD, a boosted voltage exceeding “external voltage VDD+Vt” must be applied to the gate of the NMOS transistor in order to read or write the external voltage VDD from or to a cell or a bit line. Accordingly, a high voltage VPP is generated by pumping the external voltage VDD.
However, if the level of the high voltage VPP is lower than the level of the external voltage VDD, the pumping operation for the high voltage VPP may be insufficiently performed. Accordingly, before the level of the external voltage VDD is increased to the level of the target voltage, that is, in a power up section, the high voltage VPP is electrically connected to the external voltage VDD such that the level of the high voltage VPP is increased corresponding to the level of the external voltage VDD.
FIG. 1 is a block diagram showing a conventional high voltage compensation circuit.
As shown in FIG. 1, the conventional high voltage compensation circuit includes a power up signal generator 10 and a high voltage compensation unit 12. The power up signal generator 10 generates a power up signal pwrup. The high voltage compensation unit 12 electrically connects a high voltage VPP to an external voltage VDD in response to the power up signal pwrup.
The power up signal generator 10 generates a power up signal pwrup which rises corresponding to the level of the external voltage VDD before the level of the external voltage VDD reaches the level of a target voltage, that is, during a power up section. The power up signal pwrup shifts from the high level to a low level, after the level of the external voltage VDD reaches the level of the target voltage. Such a power up signal pwrup is input into the high voltage compensation unit 12 so that the high voltage VPP is electrically connected to the external voltage during the power up section. Accordingly, the level of the high voltage VPP increases corresponding to the level of the external voltage VDD. Then, after the level of the external voltage VDD reaches the level of the target voltage, the high voltage VPP is electrically disconnected from the external voltage VDD, and the high voltage VPP is pumped through a high voltage pumping circuit (not shown).
The conventional high voltage compensation circuit can adjustably compensate for the level of the high voltage VPP in the power up section when a single-type external voltage VDD is input. However, if first and second external voltages VDD1 and VDD2 having different types are input, the conventional high voltage compensation circuit cannot properly deal with the external voltages. In other words, as shown in FIG. 2, when the high voltage VPP is electrically connected to the first external voltage VDD1 in a power up section, the level of the high voltage VPP becomes lower than the level of the second external voltage VDD2 in a section A. In addition, when the high voltage VPP is electrically connected to the second external voltage VDD2, the level of the high voltage VPP becomes lower than the level of the first external voltage VDD1 in a section B. When the level of the high voltage VPP is lower than the level of the first external voltage VDD1 or the level of the second external voltage VDD2, latch up may occur.